Generally, an audio output amplifier for power amplifying an audio signal to drive a load such as, for example, a speaker or the like employs a class-D amplifier, wherein 4 switching devices such as, for example, CMOS transistors or the like are connected in a bridge configuration for improving power efficiency.
The 4 switching devices constituting the bridge section perform pulse width modulation in response to the input audio signal using a pulse width modulator (PWM) for ON/OFF controlling the bridge control circuit by the pulse width modulated signal. The ON/OFF control of the switching devices drives highly efficiently the load such as the speaker or the like.
There are two typical pulse width modulation schemes, one is an analog modulation scheme using an analog triangle wave and the other is a digital modulation scheme using a reference clock signal. The former, i.e., the analog modulation scheme is able to continuously control the pulse width. On the other hand, the latter, i.e., the digital modulation scheme is able to perform discretely pulse width modulation depending on the reference clock. Also, in case of the digital modulation scheme, there is a need for a high reference clock frequency in proportion to the number of values to be expressed. However, as the reference clock frequency becomes higher, associated circuits become expensive and more noise is generated. It is therefore preferable to realize a pulse width modulation technique capable of expressing as many values as possible using the lowest possible reference clock frequency.
Various conventional techniques on the pulse width modulation for such digital audio amplification or the like are disclosed. See, for example, JP-7-94965A (page 2, FIG. 1) and JP-10-303657A (pages 3-4, FIG. 1).
Incidentally, in the digital pulse width modulation scheme, there are a single-side modulation scheme and a both-side modulation scheme. FIG. 6 is a timing chart for the purpose of describing the basic operation of the single-side modulation scheme. In the single-side modulation scheme, pulse width is modulated at only one side (for example, the falling portion) in the pulse width modulation (PWM) period. In FIG. 6, the horizontal axis represents time, particularly 1 PWM period corresponding to first˜eighth reference clocks, while patterns “0”˜“8” are shown in the vertical direction. Pulse width modulated pulses are modulated at the falling portions, while fixing the rising portions (or start points). In case of the pattern “0”, an “L (or low)” level continues over the entire period of the first˜eighth reference clocks, thereby outputting no pulse. In case of the pattern “1”, a pulse having the width equal to 1 reference clock is outputted in the first reference clock period. In case of the pattern “2”, a pulse having the width equal to 2 reference clocks is outputted in the first and second reference clock periods. Similarly, in case of the pattern “3”, a pulse having the width equal to 3 reference clocks is outputted in the first˜third reference clock periods. In case of the pattern 4, a pulse having the width equal to 4 reference clocks is outputted in the first˜fourth reference clock periods. In case of the pattern 5, a pulse having the width equal to 5 reference clock is outputted in the first˜fifth clock periods. In case of the pattern 6, a pulse having the width equal to 6 reference clocks is outputted in the first˜sixth reference clock periods. In case of the pattern 7, a pulse having the width equal to 7 reference clocks is generated in the first˜seventh reference clock periods. Finally, in case of the pattern 8, a pulse having the width equal to 8 reference clocks is outputted in the first˜eighth reference clock periods.
As apparent from the above description, in case of the single-side modulation scheme, it is possible to express the pattern “0”˜pattern “8”, 9 values (patterns) in total in the first˜eighth reference clock periods. In other words, in case of the single-side modulation scheme, it is possible to express (N+1) kinds of values in 1 PWM period comprising N reference clocks. However, since the center of the pulse energy does not remain constant depending on widths of pulse width modulation, it can not be used for high resolution applications.
On the other hand, FIG. 7 is a timing chart for the purpose of describing the operation of the both-side modulation scheme. In FIG. 7, the horizontal axis represents time, particularly 1 PWM period. In this particular example, an output pulse of either pattern “0”, “1”, “2”, “3” or “4” respectively having the width of 0, 2, 4, 6 or 8 reference clock period is outputted in 1 PWM period comprising first˜eighth reference clocks. In other words, since the pulse widths of the output pulses are multiplied by only even numbers of the reference clock period, the modulated outputs (patterns) that can be obtained are restricted to 5 (=8/2+1) in case of N=8, thereby less than the number as compared to the single-side modulation scheme. However, since the center of energy of each output pulse (pattern) is fixed to the center of the PWM period, it can be used for high resolution applications, for example, 16 bits.